module divide1(
		input [15:0]data1,
		input [15:0]data2,
		input [2:0]enable,
		input isNeg1,
		input isNeg2,
		input done,
		input reset,
		input sysclk,
		output reg [15:0]result,
		output reg isNeg,
		output reg suc); 

reg [45:0] diff;
reg [22:0] data1_temp;
reg [22:0] data2_temp;
reg [23:0] s;
reg [45:0] temp;
reg [4:0] counter;
reg [2:0] state;
reg [2:0] nstate;

parameter init = 3'b000, start = 3'b001, shift = 3'b010, waiting = 3'b011, finish = 3'b100;

initial begin
	diff = 46'b0;
	data1_temp = 23'b0;
	data2_temp = 23'b0;
	temp = 46'b0;
	counter = 5'd0;
	s = 24'b0;
	result = 16'b0;
	suc = 1'b0;
	nstate = init;
end

always @(*) begin
	state = nstate;
end

always @(posedge sysclk) begin
	if (reset) begin
		diff = 46'b0;
		data1_temp = 23'b0;
		data2_temp = 23'b0;
		temp = 46'b0;
		s = 24'b0;
		counter = 5'd0;
		result = 16'b0;
		suc = 1'b0;
		nstate = state;
		end
	else begin
		case (state)
			init: begin
				if (enable==3'b101) begin
					diff = 46'b0;
					data1_temp = 23'b0;
					data2_temp = 23'b0;
					temp = 46'b0;
					s = 24'b0;
					result = 16'b0;
					counter = 5'd0;
					suc = 1'b0;
					nstate = start;
					end
				else nstate = init;
			     end
			start: begin
				data1_temp = data1*100;
				data2_temp = {7'b0,data2};
				temp = {23'b0,data1_temp};
				s = {1'b1,~data2_temp+1'b1};
				nstate = shift;
			       end
			shift: begin
				if (counter<5'd23) begin
					diff = temp + {s,22'b0};
					if (diff[43]) temp = {temp[44:0],1'b0};
					else temp = {diff[44:0],1'b1};
					counter = counter + 1'b1;
					nstate = shift;
					end
				else begin
					isNeg = isNeg1 ^ isNeg2;
					result = temp[15:0];
					nstate = waiting;
					end
				end
			waiting: begin
							suc = 1'b1;
							nstate = finish;
						end
			finish: begin
				 if (done) begin
					suc = 1'b0;
					nstate = init;
					end
				else nstate = finish;
				end
		endcase
	end
end

endmodule
